Fabrication Processes for 2nm and Sub-2nm Semiconductor Nodes

Fabrication Processes for 2nm and Sub-2nm Semiconductor Nodes is a highly technical exploration of how the semiconductor industry is pushing transistor manufacturing to atomic-scale dimensions. Rather than being a casual overview, it reads like an advanced textbook or industry roadmap for professionals and researchers working on cutting-edge chip fabrication.

The book begins by tracing the evolution of Moore’s Law, Dennard scaling, and the transition from ITRS to IRDS roadmaps. It explains how the familiar "2nm" label is now more marketing terminology than a literal physical measurement, since no actual feature in a “2nm” transistor is truly 2 nanometers. Instead, nodes are judged by PPA — Power, Performance, and Area.

From there, it dives deep into quantum physics at the nanoscale, describing phenomena such as:

• Quantum confinement and how electron behavior changes when channels are only a few atoms thick.
• Quantum tunneling, which becomes unavoidable when gate oxides fall below ~1.5nm.
• Variability and stochastic limits, where individual dopant atoms cause device-to-device randomness.

Later chapters examine modern transistor architectures, detailing the shift from planar MOSFETs → FinFETs → GAAFETs (Gate-All-Around) → CFETs (vertical stacking of NMOS and PMOS). Each architecture is analyzed in terms of electrostatics, manufacturability, thermal constraints, and design flexibility.

Ultimately, the book argues that future scaling won’t come purely from shrinking transistors, but from 3D integration, advanced packaging, backside power delivery, and thermal-aware architecture.